全職
大學以上
面議（經常性薪資達 4 萬元或以上）
- NR & O-RAN compliant radio unit (O-RU) physical layer implementation
- Verilog/RTL design coding, synthesizing, & optimization to meet timing and area constraints
- Cooperate with algo for design modelling & performance bench marking
- Phy level & E2E level trouble shooting & debug
Theoretical and practical experience in the following fields:
• Digital signal processing (DFT, FFT, transform theory)
• Digital filter design (IIR, FIR, multirate filter, Upsampling/Downsampling, Interpolator/Decimator, Resampling)
• Experience in LTE(4G)/NR(5G) digital signal processing
• Programming in Verilog/RTL
• Excellent communication skills for project work in a team oriented, international environment
Nice-to-have skills
o Knowledge of digital front-end (DFE)
o Experience in Automatic Gain control (AGC), Automatic frequency control (AFC), timing error adjustment, and DPD (Digital Pre-Distortion)
o Experience in antenna tuner
o Familiar with 3GPP standards (WCDMA/LTE/LTE-A/5G)
新竹工作地點：竹北台元科學園區
法定項目：
福利制度：
更多說明：
注意！福利項目可能依不同職缺有所不同，實際職缺福利請依面試時與公司面談結果為準
查看薪資水平
